VSCode怎么配置verilog環境？代碼提示+自動例化+格式化插件分享

vscode怎么配置verilog環境？下面本篇文章給大家推薦三個插件，讓vscode流暢編寫verilog，三個插件可實現代碼提示+自動例化+格式化。

【推薦學習：vscode、vscode】

Verilog-HDL/SystemVerilog/Bluespec SystemVerilog

可實現功能：

• 語法高亮
• 自動例化
• 代碼提示和跳轉
• 自動補全

插件配置

如Verilog HDL/SystemVerilog插件歡迎頁的說明，支持Ctags功能：

配置步驟：

• 下載最新版vscode，舊版的有些功能不夠齊全；windows可選x64版本；

• 將ctags.exe的路徑設置到系統環境變量中；

• 插件設置中配置ctags路徑；

• 重啟vscode即可；

?可以選擇不同的編譯器

?包括：

• iverilog
• xvlog(vivado)
• modelsim

功能展示

支持verilog、SV等語法高亮。

shift+ctrl+p輸入verilog，可以直接自動例化模塊。

鼠標放在信號上，就會有聲明顯示在懸浮框中。Ctrl+左鍵，點擊信號名，自動跳轉到聲明處。光標放在信號處，右鍵選擇查看定義（快捷鍵可自行綁定），可以在此處展開聲明處的代碼，用于修改聲明十分方便，就不用再來回跳轉了。

Verilog_Testbench

可實現功能：

• 自動生成testbench?

?shift+ctrl+p輸入testbench，可以直接生成tb。然后在終端復制即可。

SystemVerilog and Verilog formatter

這款工具由谷歌推出，同時支持Verilog和System Verilog，效果非常好，支持自定義的格式化參數也很豐富。個人認為比verilog format好用。

可實現功能

• 自動格式化文件
• 自動格式化選定內容
• 自定義格式

自定義參數設置表

verible-verilog-format: usage: bazel-bin/verilog/tools/formatter/verible-verilog-format [options] [] To pipe from stdin, use ‘-‘ as .? Flags from common/formatting/basic_format_style_init.cc: ? ? –column_limit (Target line Length limit to stay under when formatting.); ? ? ? default: 100; ? ? –indentation_spaces (Each indentation level adds this many spaces.); ? ? ? default: 2; ? ? –line_break_penalty (Penalty added to solution for each introduced line ? ? ? break.); default: 2; ? ? –over_column_limit_penalty (For penalty minimization, this represents the ? ? ? baseline penalty value of exceeding the column limit. Additional penalty ? ? ? of 1 is incurred for each character over this limit); default: 100; ? ? –wrap_spaces (Each wrap level adds this many spaces. This applies when the ? ? ? first element after an open-group section is wrapped. Otherwise, the ? ? ? indentation level is set to the column position of the open-group ? ? ? operator.); default: 4; ? Flags from external/com_google_absl/absl/flags/parse.cc: ? ? –flagfile (comma-separated list of files to load flags from); default: ; ? ? –fromenv (comma-separated list of flags to set from the environment [use ? ? ? ‘export FLAGS_flag1=value’]); default: ; ? ? –tryfromenv (comma-separated list of flags to try to set from the ? ? ? environment if present); default: ; ? ? –undefok (comma-separated list of flag names that it is okay to specify on ? ? ? the command line even if the program does not define a flag with that ? ? ? name); default: ; ? Flags from verilog/formatting/format_style_init.cc: ? ? –assignment_statement_alignment (Format various assignments: ? ? ? {align,flush-left,preserve,infer}); default: infer; ? ? –case_items_alignment (Format case items: ? ? ? {align,flush-left,preserve,infer}); default: infer; ? ? –class_member_variable_alignment (Format class member variables: ? ? ? {align,flush-left,preserve,infer}); default: infer; ? ? –compact_indexing_and_selections (Use compact binary expressions inside ? ? ? indexing / bit selection operators); default: true; ? ? –distribution_items_alignment (Aligh distribution items: ? ? ? {align,flush-left,preserve,infer}); default: infer; ? ? –enum_assignment_statement_alignment (Format assignments with enums: ? ? ? {align,flush-left,preserve,infer}); default: infer; ? ? –expand_coverpoints (If true, always expand coverpoints.); default: false; ? ? –formal_parameters_alignment (Format formal parameters: ? ? ? {align,flush-left,preserve,infer}); default: infer; ? ? –formal_parameters_indentation (Indent formal parameters: {indent,wrap}); ? ? ? default: wrap; ? ? –module_net_variable_alignment (Format net/variable declarations: ? ? ? {align,flush-left,preserve,infer}); default: infer; ? ? –named_parameter_alignment (Format named actual parameters: ? ? ? {align,flush-left,preserve,infer}); default: infer; ? ? –named_parameter_indentation (Indent named parameter assignments: ? ? ? {indent,wrap}); default: wrap; ? ? –named_port_alignment (Format named port connections: ? ? ? {align,flush-left,preserve,infer}); default: infer; ? ? –named_port_indentation (Indent named port connections: {indent,wrap}); ? ? ? default: wrap; ? ? –port_declarations_alignment (Format port declarations: ? ? ? {align,flush-left,preserve,infer}); default: infer; ? ? –port_declarations_indentation (Indent port declarations: {indent,wrap}); ? ? ? default: wrap; ? ? –port_declarations_right_align_packed_dimensions (If true, packed ? ? ? dimensions in contexts with enabled alignment are aligned to the right.); ? ? ? default: false; ? ? –port_declarations_right_align_unpacked_dimensions (If true, unpacked ? ? ? dimensions in contexts with enabled alignment are aligned to the right.); ? ? ? default: false; ? ? –Struct_union_members_alignment (Format struct/union members: ? ? ? {align,flush-left,preserve,infer}); default: infer; ? ? –try_wrap_long_lines (If true, let the formatter attempt to optimize line ? ? ? wrapping decisions where wrapping is needed, else leave them unformatted. ? ? ? This is a short-term measure to reduce risk-of-harm.); default: false; ? Flags from verilog/parser/verilog_parser.cc: ? ? –verilog_trace_parser (Trace verilog parser); default: false; ? Flags from verilog/tools/formatter/verilog_format.cc: ? ? –failsafe_success (If true, always exit with 0 status, even if there were ? ? ? input Errors or internal errors. In all error conditions, the original ? ? ? text is always preserved. This is useful in deploying services where ? ? ? fail-safe behaviors should be considered a success.); default: true; ? ? –inplace (If true, overwrite the input file on successful conditions.); ? ? ? default: false; ? ? –lines (Specific lines to format, 1-based, comma-separated, inclusive N-M ? ? ? ranges, N is short for N-N. By default, left unspecified, all lines are ? ? ? enabled for formatting. (repeatable, cumulative)); default: ; ? ? –max_search_states (Limits the number of search states explored during line ? ? ? wrap optimization.); default: 100000; ? ? –show_equally_optimal_wrappings (If true, print when multiple optimal ? ? ? solutions are found (stderr), but continue to operate normally.); ? ? ? default: false; ? ? –show_inter_Token_info (If true, along with show_token_partition_tree, ? ? ? include inter-token information such as spacing and break penalties.); ? ? ? default: false; ? ? –show_largest_token_partitions (If > 0, print token partitioning and then ? ? ? exit without formatting output.); default: 0; ? ? –show_token_partition_tree (If true, print diagnostics after token ? ? ? partitioning and then exit without formatting output.); default: false; ? ? –stdin_name (When using ‘-‘ to read from stdin, this gives an alternate ? ? ? name for diagnostic purposes. Otherwise this is ignored.); ? ? ? default: “”; ? ? –verbose (Be more verbose.); default: false; ? ? –verify_convergence (If true, and not incrementally formatting with ? ? ? –lines, verify that re-formatting the formatted output yields no further ? ? ? changes, i.e. formatting is convergent.); default: true;Try –helpfull to get a list of all flags or –help=substring shows help for flags which include specified substring in either in the name, or description or path.

插件配置

如果是windows，systemverilogFormatter.veribleBuild設置為win64

systemverilogFormatter.commandLineArguments可以自定義格式化參數，下面放上我自己用的參數，可以實現大部分常用代碼段實現對齊。

--indentation_spaces=4?--named_port_alignment=align??--ort_declarations_alignment=align?--module_net_variable_alignment=align

如何使用？如何格式化？

和vscode內置格式化一樣，直接shift+ctrl+f就可以格式化文件，ctrl+k可以格式化選定內容。

值得注意的是，由于這個插件也是在完善中，還是存在部分問題的。

比如else不會換行。

比如，存在語法問題，或者不能識別語法的時候，格式化會使用不了。這里我將最后一個端口加上”,”就不能格式化了。

更多關于VSCode的相關知識，請訪問：vscode！